1. Field of the Invention
The invention relates generally to memory systems and more particularly to systems and methods for stretching clock cycles of the internal clock signal of a memory array macro to allow more time for a data access in the macro than the period of an external clock signal.
2. Related Art
There is a constant demand in the field of integrated circuit design for increased computational power, improved reliability, reduced cost, reduced power consumption and so on. These goals are achieved in various ways, such as by improving the physical characteristics of the devices. For example, computational power may be increased by developing components that can operate at higher clock speeds than previous components. Component sizes can also be reduced to provide additional computational power, as well as to reduce power consumption.
Size reductions and speed increases, however, are limited by such factors as available process technologies, noise, etc. These factors can, in turn, limit the performance of logic components and larger systems that incorporate these components, such as processors, memory systems, and the like. For example, the components that make up a memory system require some minimum amount of time to perform the various functions that are involved in a memory access (e.g., asserting/deasserting signals, switching transistors on/off, sensing data, etc.) If it is desired for the memory system to be able to perform one data access each clock cycle, the minimum required time to perform a data access the fines and minimum clock period, and consequently a maximum clock rate that can be used. Because it is difficult (and complicated) to design a memory system that uses a clock rate which is different than that used by other systems that access the memory (e.g., processors), this limits the speed of the other systems as well.
Various techniques have been used in an effort to alleviate this problem and to allow devices to operate at faster clock rates despite the limitations of the associated memory systems. For instance, some designs stretched the clock cycle that controlled memory accesses by buffering a global clock signal and passing data rising edge at the beginning of a clock cycle through to the memory system, but delaying the rising edge at the end of the clock cycle. As a result, the period of the clock cycle seen in the memory system was longer than the period of the global clock signal. The global clock signal could therefore be increased to a speed that was higher than could actually be used (without modification) by the memory system. There are, however, limits to the delay that can be accommodated in stretching the internal clock cycle without causing errors in the interaction between the memory system and the other systems of the device.
It would therefore be desirable to provide systems and methods for allowing even faster clock rates to be used external to the memory system, while still allowing the memory system sufficient time to access data in a single clock cycle.